Relationship Between Love And Friendship Essay - 1914 Words

When discussing love, people generally think about the love between a husband and wife, or the love between a couple in a romantic partnership, and that is one type of love that I will be discussing. In addition to romantic love, there are other types of love also. There is the love we have for our children, our families, and also the love that we have for our friends. All of these types of love share some of the same attributes, however, they have differences also. In reading and researching different types of love, I have found that romantic love and friendship seem to be the most similar in nature, although they have differences, they share a lot of the same attributes. I found that friendship and romantic love tend to have more similarities than differences. In this paper I will examine romantic love and friendship. I will discuss the definitions of the two, and what elements each of these have. I will discuss the different theories of love, and I will compare and contrast the si milarities and differences between romantic love and friendship. By friendship, I mean true friendship, or close friendships. I believe that true friendship is very different from causal friendships. True friendships involve a level of emotional intimacy that you do not find with causal friendships or acquaintances. If you look in the dictionary, it will define friendship as the relationship between friends, or the state of being friends (Merriam-Webster.com). I do not find that theShow MoreRelatedFriendship, Love, And Love1401 Words   |  6 PagesFriendship and romantic love are two of the most fundamental relationships that human beings engage in. As social animals, most humans are naturally drawn to form bonds of affection with other people. Both friendship and love, however, are difficult to fully define and conceptualize. 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Love here does not refer to romantic emotion exclusively; â€Å"love† means connection and empathy with another being. The female relationships in the poem, between Hermia and Helena, and Titania and her fairies, exist with a love based on connections between the females. However, the lovers’ relationships arise from a love produced by desire for another’s differences. The females produceRead More Ciceros De Amicitia Essays1263 Words   |  6 Pagesthe topic of friendship and how it relates to death. The word amicitia comes from the Latin root word amor which is translated to mean â€Å"love†. In this day and age the word friendship has taken on a slightly different meaning from the ancient meaning. Cicero’s De Amicitia seeks to define what friendship is, its characteristics and principles. He has challenged us to reconsider what constitutes a true friend. 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It presents a crisscrossing mash-up of various combinations of traditional love categories: friendly (plutonic or nonsexual) love, family love, lust, master/servant or apprentice/teacher love, etc. Besides being entertaining, Boogie Nights presents these combinations to provoke an insight on our part into the nature of love. This insight is exemplified in Jack’s notion of the ideal pornographicRead MoreThe Principles of Power and Conflict in relationship1502 Words   |  7 PagesMr. Baker Communication 2 4 Nov. 2013 The Principles of Power and Conflict in Relationships As relationships are formed we establish power dominances in any kind of relationship such as friendship, love, family, and in the workplace. I believe that the roles of who has power are changing in every type of relationship. Change might be welcome but as roles are changing not all support changes in the relationships such as in the workplace, and family. The principle of power comes in play most of

Information on Self Nude Shooting Free Essays

Group paper Self-nude-shooting ————————————————- Content Page 1. Introduction 3 2. Definition of self-nude-shooting 3 3. We will write a custom essay sample on Information on Self Nude Shooting or any similar topic only for you Order Now Reasons of the popularity of self-nude-shooting 4-6 4. Social impact of self-nude-shooting 7-8 5. Mindset of posting or sharing the photos/videos 9 6. The views from different parties in the society 10-11 7. Concluding remarks 12 8. References 13 9. Appendix 13 Introduction: Definition of self-nude-shooting: Self nude-shooting means individual records his/her nude body via some kinds of medium, such as cameras. And the body is shown on photos or videos. Reasons of the popularity of self-nude-shooting: It is found that self-nude-shooting is popular in Hong Kong. The reasons behind has been classified in 4 areas, which are the advancing technology, culture and people belief, the psychological condition of teenagers altered by puberty, and the satisfaction of sexual desires and misunderstandings between couples. * Advancing technology Self-nude-shooting can be carried out through several medium, such as taking photos or recording videos. When people still need a traditional camera to take photos, they needed to print the photo in shop. Compare to nowadays, people can take pictures or videos simply by a digital camera, webcam or even mobile phones and then upload to their own computer as personal collection. This big progress has encouraged people to make a record on any â€Å"memorable† moments. What’s more, the privacy has increased theoretically, thus, people would like to take photos with less ethical limits. This has explained how self-nude-shooting appears. Furthermore, communicating tool is well-developed and widely used these days. Besides putting photos into photo album, people share their photos online. They can post photos in some photo-sharing websites including blogs such as Xanga and YahooBlog, online albums like Flickr. com and Fotop. Net. If they want more interaction from others, they can even upload to the social networking website like Facebook and MySpace. If people post some striking photos, it can attract others’ attentions and get a higher click rate. Some people may gain fulfillment when people are interested in their photos. Culture and people belief The culture of a society has affected people thinking and belief. It is found that self-nude-shooting is popular especially in teenagers. After our discussion, we think that celebrity endorsement has a major impact on people. Edison Chan, the actor, is one of the infamous self-nude-shooting stars in Hong Kong. Even though the media has a cruel criticize towards his behavior, some of the teenagers view his doing as a heroic manner. Some teens appreciate his bravery. * The psychological condition of teenagers altered by puberty Puberty has a great impact on teenagers’ mental condition. During puberty, gonad will produce varies of hormones such estrogen and androgen which stimulate growth and maturate the reproductive system. What’s more, the hormones also affect the emotion. During adolescence, teenagers are more likely to make friends. They started to view their friends and influencing one another. They hope they are be respected and not to be alone. In order to join the peer group, they are asked to behave similarly. This also creates the peer pressure. For example, if their friends are doing self-nude-shooting, they maybe also asked to do t to show their friendship. * The satisfaction of sexual desires and misunderstandings between couples Teenagers are usually curious about the opposite sex. Therefore, their lovers may be the first sources to explore the sex directly. It is found that the people tend to think that showing-off good sexual ability is one way to please their partner. What’s more, during sexual intercourse, they hope they can please t heir partner by using different positioning in order to make more sexual excitement. However, we think this is inappropriate to seek for prolong healthy relationship. A healthy relationship should build beyond caring and respectful connection. Social impact of self-nude-shooting Teenagers and students: * Affect their attitude towards sex: 1. Immature teenagers or students imitate obscene movements. 2. Some of them trust what they see and hear on the internet without recognize what is really right or wrong. (This is because getting more and more self shoot nude pictures on the internet. They may consider this kind of behavior is normal. ) 3. As self shoot nude pictures are very popular on the internet, they can easily access this information, which affects their attitude towards sex. E. g. ome of the young people want to please their partners are willing to have nude self shooting or even photograph during sexual intercourse. 4. Encourage young people to have casual sex. (This is because those self shoot nude pictures may contain scenes of party sex or having sex with different people. ) Adult: * They imitate the obscene movement from those scenes of self shoot nude pictures or video and photograph others nude without noticing them. To the whole: * Challenge social mores. (China is a country where people are paying a lot of attention to ethics since ancient time especially the relationship between men and women. Couples must have sex in private area and our bodies should not show to the public. ) * Concept of sex has been distorted. (Sex is private. The exposed self shoot nude pictures and videos on the internet may cause illusion of open sex. ) * Infringe upon personal privacy. (Some of those shot are not voluntary or informed. ) * Distortions in gender roles. (Some of the self shoot nude photos and videos may contain homosexual sex shots. ) * As this kind of pictures or videos can be easily seen on the Internet, this affects the lives of others. (This is because not Internet users accept those pictures and video. In the long term: * People may have bad attitude towards sex. They may consider sex is open and casual. * This encourages the development of pornography. * People may get addicted to that pornography. * Social mores are being challenged. Example: Social impact of Edison Chen photo scandal * The scandal has shocked the general public and ignited debate about sexual morality. * The blanket coverage of the local press, their reporting style, and the appearance of photographs has also been met with public complaints to TELA. (TELA suspected that at least two journals violated the Obscene Articles Ordinance. * The images reached China mostly through an image-sharing service on Baidu (Tieba). * Beijing Network News Council (BNNC) held a meeting on 18 February to discuss the â€Å"romantic pictures†, and criticised Baidu for spreading the pictures. * Other web sites that actively discouraged the photo distribution, namely Sohu, Sina and Netease, were praised by BNCC. * People imitate to take self shoot nude photos and post on the internet. * People imitate obscene movements from those pictures. The mindset of posting or sharing the photos/videos: They want to be care, be loved and be aware. They think that posting or sharing their naked photos or videos can become a hot spot and draw the others attention. People will be notified by their acts and try to find more details about them. Also they can make new friends or attract people with other sex. People will make some comments on their photos or videos and try to make friend with them. It helps reduce their loneliness and gain the identification from other. They want to show off their sex power to the others. The main reason of this action is that they satisfy with their bodies, they want to be praised and admired by the others about their bodies and poses. Also, they try to treat themselves as observers to view back their bodies from the photos. It can be regarded as one of the sexual parahillia: exhibitionism. They find that this act is exciting, fun and safe. They are proud of their illegalized action. Besides, they think that it’s nothing matter to do this as it is a trend on the Internet, it is also safe when posting their photos or videos on their own blogs with a locked password or no one will recognize them when a nickname or anonymous name is used. Commercial reason. They can find their so call clients after posting their photos and videos on the Internet. Those clients will contact them to undergo sex services. It is well known as compensated dating. They want to fulfill their material satisfaction or gain money by means of compensated dating. The views from different parties in the society: * The public and concerned group: They deem that this act violate the tradition of moral, moral is defined as the restriction of human behaviors and the criterion for right or wrong. People showing their naked bodies to the others wantonly is obviously violating the moral as this act (posting and sharing) will definitely isturb the others, it shows no respect to the public and the naked-photo takers themselves. This kind of irresponsible behavior will badly interfere the next generation. It is easy for the children to imitate teenagers’ and adults’ action. They think that people nowadays (especially teenagers) are gradually becoming too open-minded toward sex. It seems people ignored the proper protection to their bodies. * Teachers and psychologist: Their views are similar to that of the public and concerned groups, some of the psychologists think that the reason for the action owe to the curiosity, excitation and the imitation of the others (e. g. op stars). They deemed that this action cannot prove any true love at all. The partners will be hurt mentally if the photos or videos are posted on the Internet without the consensus of them. * Parents: Parents think that people doing these kinds of behavior can be regarded as a pervert. It is the abnormal behavior. They wonder why people don’t protect their bodies and wantonly place it online. They find it hard to educate and monitor their children if this behavior becomes a trend. It is easy for the children and teenagers to browse the related websites on the Internet anytime. Thus, much time have to be spent to reeducate them. Students: Students hold different opinions toward this action. Some of the students feel the photos or videos are disgusting and it is too open-minded toward sex. They worry that if this action becomes a trend, they will blind to follow or even they will have a negative impression on friends. (They may suspect that whether their friends had taken the naked photos before. ) However, some of the students deem that it doesn’t really matter if people voluntarily take, post or share their photos and videos. We do not have the right to intervene the others’ private life. Concluding remarks: References: http://blog. lyfhk. net/kavkiskey ttp://jorliman. homedns. org/f2blog/rewrite. php/read-466. html http://www. singtao. com/yesterday/edu/0105go01. html http://jou. pccu. edu. tw/weekly/weekly1100-09/1102/deep/1102deep01. htm http://intermargins. net/Forum/2003/xiaxin/news/2002Jan-Jun/20020313a. htm http://www. 3boys2girls. com/viewthread. php? tid=203656extra=page%3D1page=13sid=NRjkDQ http://hk. knowledge. yahoo. com/question/question? qid=7008022100122 http://jou. pccu. edu. tw/weekly/weekly1100-09/1102/ deep/1102deep01. htm http://www. tcmer. com/Newscentre/shui/200802/8693. html http://news. ifeng. com/opinion/200804/0401_23_471731. shtml How to cite Information on Self Nude Shooting, Essay examples

Global Regulatory Issues for Cosmetics Industry

Question: Discuss about the Global Regulatory Issues for Cosmetics Industry. Answer: Introduction: L`Oriel is a multinational beauty and cosmetic company that is headquartered in Clichy, Hauts-de-Seine in France. L`Oreal is the largest cosmetic company in the world. The company was formed in the year 1909 by a man named Eugene Schueller and it operates in the personal care industry. The products offered by the company include; hair color, skin care products, sun protection, make-up, perfume and hair care products. The company is also involved in designs and produces products related to dermatology, toxicology, tissue engineering and bio-pharmaceutical research and product development. The company is also the single largest holder of nanotechnology patent. L`Oreal is incorporated and its listed in the Euro Stoxx stock market index. The revenue of the company in the year 2015 was 25.257 billion euros (Hisrich Kearney, 2013). The other important financial records of the company include the operating income which stood at 4.388 billion Euros and the profit of the company which was 3. 297 billion Euros. All the financial information stated above was for the 2015 financial year. The company has approximately78700 employees across the globe (Baines Fill, 2017). The company also has two subsidiaries which also specialize in manufacturing of beauty product. These subsidiaries include The Body shop and Lancome. L`Oreal has six research center located in different parts of the world. This explains the companys strong product portfolio and need driven product development. The companys current advertising slogan is because we are worth it. Company's international strategy The companys strategies are always globally focused with the company creating a globally recognizable brand. L`Oreal seeks to expend its operation further in the countries in which it does not perform so well especially in the Middle East and Africa. The expansion strategy has seen the company open new its regional offices in countries like South Africa and Nigeria. L`Oreal philosophy is to provide to the world the best and safest beauty and cosmetic products at cheap prices. The company has research and development centers in 4 countries across the globe with further plans to develop some more. Two of the development centers are in France, one in Japan, one in Shanghai China, one in India and another one in Clark, New Jersey, USA (Hisrich Kearney, 2013).. The regions for location of the research and development centers are chosen based on various factors. Some of the factors considered when decision on location of RD centers include; availability of skilled labor, availability of h ighly trained and experienced researchers, operational costs that the company will incur in this region, laws affecting research and development in the region, economic development and growth of the region as well as political stability of the area under consideration (Tungate, 2011). For an area to be chosen for location of RD center, it has to have attained all the above requirements as well as offer a suitable environment for research to thrive. L`Oreal marketing strategies The marketing strategies of L`Oreal are very effective. The company carries out proper market research before development of new products in order to identify the needs of consumers and fill the existing gap in the market. This therefore makes the marketing of the companies` products easier since it does not have to do a lot of promotion and impose the product on the customers. The customers buy the product because it fulfills their specific needs. L`Oreal sells its products in all corners of the world in both developed and under-develop countries. The companys major sales are attained mainly in Europe, China and USA (Baines Fill, 2017). There are also fast developing markets like India which form an important component of the companys customer base. Africa is also experiencing growth at a very high rate and this has provided an opportunity for the company to market it products in this region with the company gaining increased market share in this region. Therefore, the major motiva ting factors for the marketing of the companys products is the level of economic activity and development, stability of the country as well as social and religious customs of the people living in these countries. This mainly applies in Muslim dominated countries which have restrictions on use of beauty and cosmetic product. The company has diversified its products to cater for the needs of each class of customers. L`Oreal uses a variety of marketing strategies in order to achieve its marketing objectives. One of these strategies is diversification strategy. The company has developed products ranging from skin care, hair care, dermatology and toxicology products. This has provided the company with a large customer base and therefore, they are able to attain high sales volumes (Plankett Plankett, 2008). Another marketing strategy used by the company is that of product differentiation. This involves making little changes to products with similar uses in order to offer more value and choice to the consumer. L`Oreal has used this strategy especially with the skin care products. The company uses indirect distribution channels. The company sells to the wholesalers who sell to the retailers and then the retailer sells to the final consumer. Company's logistics approach L`Oreal produces its goods in various countries but its main manufacturing plant is in France. The companies` largest factory was completed in the year 2012 in Jababeka Industrial Park, Cikarang, Indonesia. The investment cost the company a total of US$100 million. Of the total production from the company, 25% will be sold within the country and the rest will be exported. The factories in France also produce a significant amount of products which are exported to other countries (Hitts Hoskinsson, 2014). Other countries where L`Oriel produces its products include China and USA. The decision by the company on where to locate its factories is influenced by a combination of factors. These factors include; the availability of skilled labor force and the cost of factors of production in the country. The factors of production considered in this case include, wage rate, cost of capital and the cost of land. The company opts to produce its products in countries where these factors are cheap in order to minimize cost and hence make more profit. Other factors that influence the selection of a country to produce goods include; political stability of the country of location, economic growth rate of the country, economic policies and foreign investment policies of the country, the level of government support to foreign investors as well as the market potential of the country in regard to the goods the company wants to produce. The combination of this factors influences the decision of the company to invest in the country of not. L'Oreal Human Resource Management Approach The companies HRM strategies advocate for fair recruitment and employment opportunities for all people irrespective of race, tribe, nationality or even religion. The company offers equal employment opportunities to people applying for jobs and recruitment, selection and hiring are all done on merit. The companys human resource policy states that the company cannot employ more than 25% of its employees from outside the country in which the factories are located. The rest of the employees for the company should be nationals of the country in which the production activities are located. The 25% or less should be only skilled workers. The locals always get consideration before the companies decides to outsource for labor. The promotion policies of the company also give locals a priority to be promoted to senior level of management based on their performance. The human resource policies of L`Oreal will be very important for this country since they are favorable to the locals. The nationals of the countries will be guaranteed of 75% of all the vacancies in the organization and therefore, this will boast the levels of employment in the country (Abdallah Albadri, 2011). Creation of employment by the company will result to reduction in the levels of poverty in the country and hence promoting improved standards of living. There are various risks that may come with the company investing in this country. One of the risks of investing in this country by L`Oreal is that the company will bring competition to the local infant industries. When L`Oreal opens its production factory in this country, the local industries that have invested in cosmetic and beauty products will suffer from the effect of competition from the giant multinational company(Alsop, 2008). This is because the company has large amount of resources at its disposal and will therefore enjoy economies of scale in its production and hence offer its products at a cheaper price. Another risk of allowing L`Oreal to invest in this country is that the country may fail to benefit much from the profits generated from local operations because the company may direct the profits realized in this country to other countries. The movement of the capital will mean that the country wont benefit fully from the use of its resources in the country and the economic impact of the invest may not be as big as expected (Jones, 2010). The environment effect of new industries by the company will also be a risk. Increasing concern for the environment in the country due to the negative effects that environmental pollution has brought to the country is a major cause for concern (Betton, 2007). The production activities of the company will bring a lot of negative environmental effects to the country and in areas which the factories will be located. Despite being several risks associated with the company investing in the country, there are also various advantages that the country will gain from the company investing in the country. One of the benefits is creation of employment opportunities. The companys human resources policies are very friendly and will promote the development of local human resources through training and experience. The locals will get employment through skilled and unskilled job opportunities (Industrial Systems Research, 2013). This will help to reduce the unemployment burden faced by the country at the moment. The company will also be paying taxes to the government. This will contribute further to economical development of the country. By investing in the country, the company will contribute positively to the society through corporate social responsibility activities of the company. Investment by the company will help to develop research and development in the country. Research in tissue engineering and biotechnology by the company will be a positive influence for the country and will encourage other companies also to invest in research and development in the country to help solve problems facing human beings. If the company in the country, it will gain by allowing exchange of human resources between countries in which the company is operating. This will promote the exchange of ideas and knowledge which will promote development in the country. Recommendations The company should be allowed to invest in the country and given all the necessary support to help them in setting up a factory. This is because of the many advantages that the investment will bring to the country compared to its shortcomings. The government should create an enabling environment for foreign investment because of the advantages that accrue from the companies investing in this country. This will be done by making laws that are friendly to foreign investors and that makes carrying out business in the country easier. Conclusion The investment by L`Oriel in the country will be a major milestone for the country because it will set a trend for other large international companies to follow by inspiring them with confidence. The country will also benefit in a big way through the employment opportunities that will be created by the investment. Among many other advantages the company will contribute greatly to the economic growth of the country by paying taxes and through many other means (Abdallah Albadri, 2011) The shortcomings that may arise with this investment include the risk of killing the local manufacturing companies through unfair competition. Another major risk is to the environment given the waste that will result from the manufacturing activities of the company. References Abdallah, S., Albadri, F. (2011). ICT acceptance, investment and organization: Cultural practices and values in the Arab world. Hershey, PA: Information Science Reference. Alsop, R. (2008). The trophy kids grow up: How the millennial generation is shaking up the workplace. San Francisco: Jossey-Bass. Academy of Marketing Science. (2008). Developments in marketing science. Greenvale, N.Y., etc: Academy of Marketing Science. Baines, P., Fill, C., Rosengren, S. (2017). Marketing Betton, C. I. (2007). Global regulatory issues for the cosmetics industry. Norwich, N.Y: W. Andrew Pub. INDUSTRIAL SYSTEMS RESEARCH. (2013). Manufacturing and Investment Around the World: An International Survey of Factors Affecting Growth and Performance. Jones, G. (2010). Beauty imagined: A history of the global beauty industry. Oxford: Oxford University Press. Hitt, M. A., Ireland, R. D., Hoskisson, R. E. (2014). Strategic management: Competitiveness globalization. Hisrich, R. D. D., Kearney, C. (2013). Managing Innovation and Entrepreneurship. Capon, N. (2007). The marketing mavens. New York: Crown Business. Guston, D. H. (2010). Encyclopedia of nanoscience and society. London: SAGE Plunkett, J. W., Plunkett Research, Ltd. (2008). Plunkett's nanotechnology MEMS industry almanac 2008: The only comprehensive guide to nanotech companies and trends. Houston, Texas: Plunkett Research, Ltd. Tungate, M. (2011). Branded beauty: How marketing changed the way we look. Philadelphia, PA: Kogan Page.

Music Lyrics Do Not Promote Violence free essay sample

Rap music can be considered a style of art, and a way for the artists to express feelings through their words on paper. However, there are quite a few rap artists that get criticized for their lyrics. In my essay, I want to discuss why rappers use certain lyrics in their music and why people shouldnt believe that it causes violence among the younger generations. People shouldnt censor the music Just because of violent, vulgar and abusive messages it promotes to the world.I believe in my own mind, that there is a reason for these types of lyrics hat rap artists use and I will simply explain those reasons in this essay. Rap has been called one of the most Important music forces to emerge In two decades. Its pounding beats and staccato rhymes exploded on the streets of the urban America In the early asses and since have become the theme music and lyrical heart of the vibrant youth culture called hip-hop ( SIRS 1993). We will write a custom essay sample on Music Lyrics Do Not Promote Violence or any similar topic specifically for you Do Not WasteYour Time HIRE WRITER Only 13.90 / page There are many different types of rap artist. There are some that talk about money, some talk about righteousness, and the list goes on and on. Every rap artist had their own way of expressing themselves. There are those that talk about sex, drugs, and violence who receive the negative attention( SIRS 1993). People, think this so- called gangster rap Is a bad Influence on children In the world and that It promotes violence and that It also Is abusive to women. Dolores Tucker, head of national congress of black women has been among those pressuring different record companies to stop distributing gangster rap music. There were other significant names that participated in this action.Names like Senate Majority leader Bob dole, and former education Secretary William J. Bennett(Surveys, pig. 1). There are some rap artists that have been openly criticized for their lyrics. Rappers Like Ill Kim, Too Short, Snoop Doggy Dog, and a member from Too Live Crew, named Luke Jaywalker. These rap artists In the past have been appointed for the things they say in their music. Ill Kim talks about sex in her music, Too Short talks about drugs, sex, and how much of a pimp he is, and Luke Jaywalker talks about girls and sex.The lyrics that these rap artist use in their music might not e suitable for everybody to listen to but I dont think their music should be banned or criticized because you dont have to listen to It If you dont choose to. Rap music, how much Influence does It really have on Its youthful listeners? Many, from record company executives to high school students agree that it plays a critical role in the lives of many tans, affecting the way they dance, dress and speak(Slurs 1993). Personally, I feel that rap music is a form of art.I think it takes a great deal of talent to write lyrics that rap artists write, because you have to use metaphors and similes, ND at the same time get your point across so the listeners can understand. I give rappers a great deal of credit because I know It took them a long time to get where their at today, and I know It takes a tremendous amount of time to write a song. Its also true and strongly agree with that rap artists use lyrics that reflect on their childhood and the way they grew up.That could be the reason why gangster rappers and rappers talk about sex, drugs, and violence in their music because that was what they were exposed to through out their life. Rap artists generally write about what they know because it is easier to write about things and situations that you know, and situations that involve those subjects. Not Just write about them in hopes to cause more violence in our world. Young rap fans caution it is wrong and simplistic to believe music can dictate their actions. Upbringing and circumstance steer a childs behavior, they say, not a record on a turntable or a performer posturing on stage(Newsweek, 1998).There are other reasons why gangster rappers should not be criticized for their lyrics. One reason is that I would rather hear gangster rappers talk about violence on the streets than them actually going out on the streets and participate in the violence. Another reason why rappers shouldnt be criticized is because the world was violent long before rap was invented, and it is not rap music that is making the world more violent then it is already. I strongly believe that people have the freedom of choice to listen to rap music and if you dont like what rap artists talk about, then you do not have to listen to the music.If people didnt have a choice hat would be one thing, but as long as people have a choice to do or not to do something then they shouldn t try to criticize it. To me, rap music is more than a strain. It is the reflection of horrible suffering, struggle and pain of the ghetto life. I feel that art reflects life, so I ask myself why arent the National Black leaders like Dolores Tucker, more concerned about where the source of rap music exists than the work denuding these types of harsh conditions(Slurs 1993). I think that kids know the difference between right and wrong, music and reality.They know its not right to go kill somebody and if there driven to that, thats not the fault of the music, says Jon Chester, editor of The Source, a rap magazine(SIRS 1993). If the people throughout the world that criticize gangster rap music would begin to really care then they would try to find and fix the conditions that this art of music comes from and stop criticizing the artist. In other words, the abusive language and rise of violence found in most gangster rap songs are the reality of our present day society. Americans should be tauter enough to realize that not talking about something wont cause it to go away. People talk about the violence of gangster rap music, but look at the violence we see on television everyday, on almost every channel you turn to. Violence is everywhere, you might see or hear something violent every day of your life, whether it is on television, radio or in real life. Violence has been existing for hundreds and hundreds of years, gangster rap music hasnt remotely made violence more intense or worse than it already is( Surveys, pig. 1).So is it then fair to pin point rap music and blame its lyrics on the violence happening around the world? Teen-eager, both black and Latino, say it is the driving beat that attracts them and many other young people to rap. That, and the musics honesty(Slurs 1993). Its not the guns and drugs that make them like the music. The rappers arent saying to solve a problem you must kill, they are Just stating what they know. In which, ever since they were young, that violence around them always ends in a shooting or stabbing, so is it right to blame them for singing about it when really they learned it from television?Sex in rap music shouldnt be criticized either because look at all the pornography that is in the world today. There are magazines that are being sold nearly everywhere. They have triple X rated movies that could be purchase and you could rent these kind of movies at your nearest video store(Showbiz, pig. 1). So, lyrics that talk about sex cant hardly be no worse than the movies and magazines being sold all over the world today. When used in their neighborhoods growing up, and maybe they had to sell drugs for a while to put food on their table( Newsweek 1998).I feel, people get confused about what the rap artist is trying to say to people. They are missing the whole point. Just because rap artists talk about drugs in their songs doesnt mean they are actually selling the drugs or using the drugs. These rap artists are making thousands of dollars Just by making records, why would they go out and sell drugs? That doesnt make any sense. There are plenty of artists that are positive, and speak positive aspects in their music about life, like A Tribe Called Quest, the Roots, De La Soul, and many others.So for those that think that rap music has a negative effect on children, and people in the world, there are a lot of rappers that speak unity, and things that are positive about life(Showbiz, pig). If a person could listen to some of these positive rap artists, they could learn about life. There have been plenty of times where I was in a terrible mood or I was upset about something, and I popped in a CD of a rapper, and after I was finished listening to the CD I felt much better. The words and phrases used, are words of actual life events and the positive things or outcomes of them.In inclusion, I speak in favor of gangster rap, and I dont think people should criticize these rap artists because they are speaking the truth. Situations theyve been in are shown through their lyrics and we need to try to find the source of the problem instead of criticizing the person speaking about the problem. Drugs, Sex, and Violence are what gangster rappers are considered to be glorifying, but drugs, sex, and violence was in effect long before rap music was even thought of and so we shouldnt use the type of music against the type of behavior caused by teens around the world. Word Count: 1667

50 Synonyms for Song

50 Synonyms for Song 50 Synonyms for Song 50 Synonyms for Song By Mark Nichol Numerous words that describe various types of musical composition are listed and defined below. (Note that in the definitions below, popular denotes not a musical form that is widely enjoyed, but a song of a type traditionally derived from common people and folk traditions rather than from professional composers. Forms of the word accompany refer to instrumental support.) 1. Air: any of several types of songs or songlike compositions, including ballads and folk songs 2. Anthem: a song or hymn of joy or praise or, by extension, a rousing pop song that resonates with a certain class of listeners 3. Aria: a complex solo accompanied melody, especially in opera 4. Art song: a solo accompanied melody often performed on a formal social occasion 5. Ballad: a narrative composition with rhythmic verse, or a popular slow romantic or sentimental song 6. Barcarole: a work song with a beat that alternates between strong and weak to suggest the rhythm of rowing a boat 7. Cantata: a composition for one or more voices with solos, duets, choruses, and speechlike parts 8. Canticle: a song based on scripture and performed during a church service 9. Carol: a song or hymn of joy, performed popularly or during a church service 10. Chanson: the type of song sung in a cabaret or a music hall 11. Chant: as monotonous but rhythmic song or other vocalization; see also plainsong 12–14Â ­. Chantey/chanty/shanty: a rhythmic sailors’ work song 15. Chorale: a hymn or song sung by a group in church 16. Cover: a song composed by someone other than the performer(s) 17. Descant: a melody sung as a counterpoint to another melody 18. Dirge: a song of mourning 19. Ditty: a simple, lighthearted popular song 20. Drinking song: an upbeat song appropriate for group singing during social drinking 21. Elegy: see dirge 22. Fight song: an inspirational song to encourage athletes during team competition 23. Folk song: a popular song with a simple melody and a verse/refrain structure 24. Glee: a part-song, generally one performed by men 25. Hallelujah: a song of praise or thanks 26. Hymn: a song of joy or praise, especially in a religious context 27. Noel: a carol sung at Christmastime 28. Jingle: a short, catchy, repetitive song, including one used to advertise a product or service 29. Lament: see dirge 30. Lay: a simple song or other ballad 31. Lullaby: a simple rhyming song sung to soothe children or prepare them for sleeping 32. Madrigal: see glee and part-song 33. Medley: two or more songs, or parts thereof, performed as one composition 34. Melody: a rhythmic composition 35. Motet: a choral composition, usually unaccompanied, based on a sacred text 36. Paean: a hymn or song of praise, thanks, or triumph 37. Part-song: a usually unaccompanied song for two or more voices, one of which carries the melody 38. Psalm: a sacred song sung during religious services 39. Remix: a variation of a song that includes additional or rearranged elements 40. Requiem: see dirge 41. Rocker: an upbeat, energetic song in the style of the rock genre 42. Round: a song in which multiple singers sing the same melody and lyrics 43. Roundelay: a simple song that includes a refrain 44. Serenade: a courting song, vocal or instrumental or both 45. Spiritual: a simple, emotional religious song of a form developed by black slaves in the American South 46. Standard: a familiar song that is among those typically performed by a certain category of musicians 47. Threnody: see dirge 48. Torch song: a popular sentimental song, usually referring to the end of a love affair or to unrequited love 49. Vocal: a song for voice accompanied by one or more instruments 50. Work song: a song structured to aid in the performance of a rhythmic group task Want to improve your English in five minutes a day? Get a subscription and start receiving our writing tips and exercises daily! Keep learning! Browse the Vocabulary category, check our popular posts, or choose a related post below:The Yiddish Handbook: 40 Words You Should Know41 Words That Are Better Than GoodEbook, eBook, ebook or e-book?

John McClernand Civil War Union Major General

John McClernand Civil War Union Major General John Alexander McClernand was born May 30, 1812, near Hardinsburg, KY. Moving to Illinois at a young age, he was educated in local village schools and at home. First pursuing an agricultural career, McClernand later elected to become a lawyer. Largely self-educated, he passed the Illinois bar exam in 1832. Later that year McClernand received his first military training when he served as a private during the Black Hawk War. A devout Democrat, he founded a newspaper, the Shawneetown Democrat, in 1835 and the following year was elected to the Illinois House of Representatives. His initial term lasted only a year, but he returned to Springfield in 1840. An effective politician, McClernand was elected to the US Congress three years later. The Civil War Nears During his time in Washington, McClernand violently opposed the passage of the Wilmot Proviso which would have banned slavery in the territory acquired during the Mexican-American War. An anti-abolitionist and staunch ally of Senator Stephen Douglas, he aided his mentor in passing the Compromise of 1850. Though McClernand left Congress in 1851, he returned in 1859 to fill the vacancy caused by the death of Representative Thomas L. Harris. With sectional tensions rising, he became a firm Unionist and worked to advance Douglas cause during the election of 1860. After Abraham Lincoln was elected in November 1860, Southern states began leaving the Union. With the beginning of the Civil War the following April, McClernand commenced efforts to raise a brigade of volunteers for operations against the Confederacy. Eager to maintain a wide base of support for the war, Lincoln appointed the Democratic McClernand a brigadier general of volunteers on May 17, 1861. Early Operations Assigned to the District of Southeast Missouri, McClernand and his men first experienced combat as part of Brigadier General Ulysses S. Grants small army at the Battle of Belmont in November 1861. A bombastic commander and political general, he quickly irritated Grant. As Grants command was expanded, McClernand became a division commander. In this role, he took part in the capture of Fort Henry and Battle of Fort Donelson in February 1862. At the latter engagement, McClernands division held the Union right but failed to anchor its flank on the Cumberland River or another strongpoint. Attacked on February 15, his men were driven back nearly two miles before Union forces stabilized the line. Rescuing the situation, Grant soon counterattacked and prevented the garrison from escaping. Despite his error at Fort Donelson, McClernand received a promotion to major general on March 21. Seeking Independent Command Remaining with Grant, McClernands division came under heavy attack on April 6 at the Battle of Shiloh. Helping to hold the Union line, he took part in the Union counterattack the next day which defeated General P.G.T. Beauregards Army of the Mississippi. A constant critic of Grants actions, McClernand spent much of the middle of 1862 conducting political maneuvering with the goal of either displacing Major General George B. McClellan in the east or obtaining his own command in the west. Obtaining a leave of absence from his division in October, he traveled to Washington to lobby Lincoln directly. Desiring to maintain a Democrat in a senior military position, Lincoln ultimately granted McClernands request and Secretary of War Edwin Stanton gave him permission to raise troops in Illinois, Indiana, and Iowa for an expedition against Vicksburg, MS. A key location on the Mississippi River, Vicksburg was the last obstacle to Union control of the waterway. On the River Though McClernands force initially only reported to Union General-in-Chief Major General Henry W. Halleck, efforts soon commenced to limit the political generals power. This ultimately saw orders issued for him to take command of a new corps to be formed out his current force once he united with Grant who was already operating against Vicksburg. Until McClernand rendezvoused with Grant, he would remain an independent command. Moving down the Mississippi in December he met Major General William T. Shermans corps which was returning north after its defeat at Chickasaw Bayou. The senior general, McClernand added Shermans corps to his own and pressed south aided by Union gunboats led by Rear Admiral David D. Porter. En route, he learned that a Union steamer had been captured by Confederate forces and taken to Arkansas Post (Fort Hindeman) on the Arkansas River. Re-routing the entire expedition on Shermans advice, McClernand ascended the river and landed his troops on January 10. Attackin g the next day, his troops carried the fort in the Battle of Arkansas Post. Issues With Grant This diversion from the effort against Vicksburg greatly angered Grant who saw operations in Arkansas as a distraction. Unaware that Sherman had suggested the attack, he complained loudly to Halleck about McClernand. As a result, orders were issued allowing Grant to take complete control of the Union troops in the area. Uniting his forces, Grant shifted McClernand into command of the newly-formed XIII Corps. Openly resentful of Grant, McClernand spent much of the winter and spring spreading rumors regarding his superiors supposed drinking and behavior. In doing so, he earned the enmity of other senior leaders such as Sherman and Porter who saw him as unfit for corps command. In late April, Grant elected to cut loose from his supply lines and cross the Mississippi south of Vicksburg. Landing at Bruinsburg on April 29, Union forces pressed east towards Jackson, MS. Turning towards Vicksburg, XIII Corps was engaged at the Battle of Champion Hill on May 16. Though a victory, Grant believed that McClernands performance during the battle was lacking as he had failed to press the fight. The next day, XIII Corps attacked and defeated Confederate forces at the Battle of Big Black River Bridge. Beaten, Confederate forces withdrew into the Vicksburg defenses. Pursuing, Grant mounted unsuccessful assaults on the city on May 19. Pausing for three days, he renewed his efforts on May 22. Attacking all along the Vicksburg fortifications, Union troops made little headway. Only on McClernands front was a foothold gained in the 2nd Texas Lunette. When his initial request for reinforcements was declined, he sent Grant a misleading message implying that he had taken two Confederate forts and that another push might win the day. Sending McClernand additional men, Grant reluctantly renewed his efforts elsewhere. When all of the Union efforts failed, Grant blamed Mc Clernand and cited his earlier communications. With the failure of the May 22 assaults, Grant commenced a siege of the city. In the wake of the assaults, McClernand issued a congratulatory message to his men for their efforts. The language used in the message sufficiently angered Sherman and Major General James B. McPherson that they lodged complaints with Grant. The message was also printed in Northern newspapers which was in contravention of War Department policy and Grants own orders. Having been constantly annoyed with McClernands behavior and performance, this breach of protocol gave Grant the leverage to remove the political general. On June 19, McClernand was officially relieved and command of XIII Corps passed to Major General Edward O. C. Ord. Later Career Life Though Lincoln backed Grants decision, he remained cognizant of the importance of maintaining the support of Illinois War Democrats. As a result, McClernand was restored to command of the XIII Corps on February 20, 1864. Serving in the Department of the Gulf, he battled illness and did not take part in the Red River Campaign. Remaining in the Gulf for much of the year, he resigned from the army due to health issues on November 30, 1864. Following the assassination of Lincoln the following year, McClernand played a visible role in the late presidents funeral proceedings. In 1870, he was elected circuit judge of the Sangamon District of Illinois and remained in the post for three years before resuming his law practice. Still prominent in politics, McClernand presided over the 1876 Democratic National Convention. He later died on September 20, 1900, in Springfield, IL and was buried at citys Oak Ridge Cemetery. Selected Sources History of War: John A. McClernandUS Congress: John A. McClernandMr. Lincoln Friends: John A. McClernand

Business Decision Malkng Projects, Part 3 Essay Example | Topics and Well Written Essays - 250 words

Business Decision Malkng Projects, Part 3 - Essay Example ft. in size. Thehomesaveragedthreebedroomsandtwobathswhile 30% of thehomeshave a pool. Of the 30 homes, 70% had a garageandtheaveragedistance from thecitycenter is 15 miles(Simon, 1979). There are manyadvantagesandopportunities in businessownershipthat may includeFlexibility, freedom, being your boss, andcontrol to create your future. Lack of self-discipline, however, createschances of businessfailure. Datainformationhavingbeenobtained from varioussourcesgaveinsight to thecurrenthappenings in thebusinessworld. Thechoice of opening a franchise is a significantbusinessdecision, andmanyrisks can be laid to restif there is sufficient data analyzed to makesurethechoice is going to be successfulandprofitable(Cooper & Schindler, 2003). Knowledge of commercialrealestateandfinancemarkettrendshelps Century 21 to establish its franchiseandto preparefor long-term survivability and profitability. After validating and analyzing the housing statistics and confirming the reliability, starting a new franchise in the identified new community is the final step to be

Important Assignment about Micro economics Example | Topics and Well Written Essays - 2000 words

Important about Micro economics - Assignment Example In international business, outdoing the production of a country remains impossible as it does not relate on the national scale. Comparative advantage applies in businesses, but when it comes to doing business across the borders a nation considers more than one business. Comparative advantage and absolute advantage are two different aspects. The article compares the absolute advantage of Bangladesh and U.S. Bangladesh cannot produce more goods per unit in comparison to the United States but they can produce goods per unit at a lower price. Comparative and absolute advantage does not hinder countries from conducting business. For instance, Bangladesh may have a comparative advantage in the production of sewing garments, even if Americans can produce better. They both benefit if Americans outsource the production from Bangladesh. American can then focus on producing products that they are far much better in producing. The two economies hence grow through interaction and exposure in doin g business. Comparative and absolute advantage plays an important role in regulating product production across boundaries. According to the article, the limit to which a country retracts production depends on the goods and services in question. A country remains in comparative and absolute advantage if the regulation of production maintains. ... or services below the expected target Application The article indicates a shortage of gas in Mexico due to the surplus production in the United States. The move leads Mexico to reduce the supply of gas to its market consumers with a great margin. A surplus by the United States in the production of gas effects on the energy based companies. Main contractors including Pemex reduce their gas supplies to deal with the surplus through measures set on every producing company. Mexico hence faces a shortage due to the production boom in the United States. The relation between the U.S. and Mexican rates led to the price of gas lowering. This led to a decrease in the wholesale price hindering manufacturers from obtaining the required amount of energy. A surplus in production of gas means the two countries have to utilize the excess amount of gas in the market before producing more gas. Mexico hence suffers a shortage after its home based companies reduce the level of production. In market anal ysis, the problem arises from pricing as opposed to penalties and pipelines. The increase in imports into the Mexican market makes gas available for the local market at a cheaper price as compared to the gas offered through the local production. It becomes logical for businesses to purchase the imported, cheap gas as compared to the expensive, local produced gas. Supply and demand depends on the readily available market for selling products and services. Link: http://au.ibtimes.com/articles/381641/20120907/surplus-shale-leads-gas-shortage-mexico.htm Chapter 4: Consumer and Producer Surplus Chapter 4 terms Consumer surplus: Consumer surplus is a measure of consumer satisfaction where customers are willing to spend more on a product than the stated market price. . Producer surplus: Producer

Ping Sweeps and Port Scans Essay Example for Free

Ping Sweeps and Port Scans Essay This report is to provide insight on nefarious computer activities called ping sweeps and port scans as a request from management. I will identify them, explain what they are use for, how they are used and how to stop them from attacking a network. Finally I will discuss how they can be eliminated as security risk. The information in this report is designed to increase the understanding and knowledge of these two activities so that this company’s IT department will be in a better position to recognize them and block potential attacks from their use. According to S. Branch (2012), in his article What is a Ping Sweep he says â€Å"A ping sweep, also called an Internet Control Message Protocol (ICMP) sweep, is a diagnostic technique used in computing to see what range of (IP) addresses are in use by live host, which are usually computers†. Ping sweeps are not unusual, they are often used by administrators in diagnosing network issues; however, hackers also use ping sweeps to find active computers so they will know where to concentrate their attacks. This can become a serious security breach for an unprepared network. Hackers send not one ping but many packets at the same time. This tends to slow down a network. When the hackers ping sweep finds an active computer it can send request for confidential information. There is no reason to be alarmed by ping sweeps because the solution for stopping them is very simple. The system administrator only need to disable ICMP packets and if the system administrator wants to do a ping sweep, just enable the ICMP packets temporarily. According to S. Branch (2012), â€Å"ping sweeps are older and slower technology, and are not in use as much as in the past†. A port scan attack is a popular reconnaissance technique that attackers use to discover services they can break into according to Yahoo Answers (2007), Author unknown. Yahoo Answers states that â€Å"All machines connected to a network run many services that use TCP or UDP ports and there are more than 6000 defined ports available. Normally port scan does not make direct damage just by port scanning. Potentially a port scan helps the attacker find which ports are available to launch various attacks†. A port scan sends a message  to each port one at a time. The response received back indicates whether the port is being used and if so, the port will be probed for weakness. TCP ports are the most attacked ports because they are connected oriented and give good feedback to the attacker. The most frequent port scan attacks to look for are: Stealth Scan, which is design to be undetected by auditing tools, SOCKS, which allows multiple machines to share a common internet connection, easy access when not configured correctly. Bounce Scans, are systems that they can bounce their attacks through. These systems are FTP server, Email server, HTTP Proxy, Finger and others. These all have vulnerabilities to do bounce scans. They also use UDP ports to find open ports, but it is not often used because it is easily blocked. Port Scan attacks can be reduced or completely solved by deploying Firewalls at critical locations of a network to filter unwanted traffic. There is also Port Scan Attack Detectors (PSAD) on the market for free use. In the fast developing world of computer technologies there will always be hackers and other types looking for ways to still. In the earlier days of computer technology they were not much of a problem if any. Today programmers and system builders program and build their goods with hackers and others in mind. Many security features are built in and other features are discussed and put in place at the beginning of the project. Nothing is foolproof, but if there is a way for them to get in, there is a way to keep them out. References Author unknown. (2007). What is a Port Scan Attack? : Yahoo Answers http://answers.yahoo.com/question/index?qid=20061105020422AAtre1p Branch S. (2012). What is a Ping Sweep? :  © 2003-2013 Conjecture Corporation http://www.wisegeek.com/what-is-a-ping-sweep.htm

The Limits of Language in Heart of Darkness Essay -- Literary Analysis

The Limits of Language in Heart of Darkness From the very beginning of Heart of Darkness, Joseph Conrad traps us in a complex play of language, where eloquence is little more than a tool to obscure horrific moral shortcomings. Hazy, absurd descriptions, frame narratives, and a surreal sense of Saussurean structural linguistics create distance from an ever-elusive center, to show that language is incapable of adequately or directly revealing truth. Understanding instead occurs in the margins and along the edges of the narrative; the meaning of a story â€Å"is not inside like a kernel but outside, enveloping the tale which brought it out only as a glow brings out a haze† (105). The title of the novel is itself misleading, because Conrad purposely leads us around understanding rather than directly to its heart, always hinting at something that, it seems, cannot be expressed. En route to â€Å"the biggest...most blank† space on the map of his youth, Marlow muses: â€Å"My isolation amongst all these men with whom I had no point of contact, the oily and languid sea, the uniform sombreness of the coast, seemed to keep me away from the truth of things, within the toil of a mournful and senseless delusion† (108, 114). He repeats words until they are nothing but sounds, polysyllabic mouthfuls devoid of real meaning: â€Å"palpable,† â€Å"inestimable,† â€Å"inscrutable,† â€Å"impenetrable.† Thick layers of images accumulate until all senses are enshrouded in mist, darkness, and distance. And yet, even in the face of the Unknowable, there is still an adamantly declared sense of understanding, however elusive or inadequat e it may be. Marlow recalls that his experience in the Congo, for example, â€Å"seemed somehow to throw a kind of light on everything about me — and into ... ...ose of the earth,† according to the Saussurean linguistic theory that Conrad seems to support. â€Å"There was nothing either above or below him,† Marlow observes, â€Å"and I knew it... I †¦ did not know whether I stood on the ground or floated in the air.† In his essay, â€Å"The Failure of the Imagination,† James Guetti writes that in Heart of Darkness, language has meaning â€Å"in terms of the exterior of experience — the coast of a wilderness, the surface of a river, a man's appearance and his voice — and the meaning can exist as a reality so long as one remains ignorant, deliberately or otherwise, of all that lies beyond these exteriors, of what language cannot penetrate. For with the intimation that there is something beyond verbal, and indeed, intellectual capacities, comes the realization that language is fiction† (SOURCE). Perhaps this is the ultimate horror.

Time to Digital Converter Used in All Digital Pll

Master Thesis ICT Time to Digital Converter used in ALL digital PLL Master of Science Thesis In System-on-Chip Design By Chen Yao Stockholm, 08, 2011 Supervisor: Dr. Fredrik Jonsson and Dr. Jian Chen Examiner: Prof. Li-Rong Zheng Master Thesis TRITA-ICT-EX-2011:212 1 ACKNOWLEDGEMENTS I would like to thank: Professor Li-Rong Zheng for giving me the opportunity to do my master thesis project in IPACK group at KTH. Dr. Fredrik Jonsson for providing me with the interesting topic and guiding me for the overall research and plan. Dr.Jian Chen for answering all my questions and making the completion of the project possible. Geng Yang, Liang Rong, Jue Shen, Xiao-Hong Sun in IPACK group for the discussion and valuable suggestions during the thesis work. My mother Xiu-Yun Zheng and my husband Ming-Li Cui for always supporting and encouraging me. i ABSTRACT This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters.Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. The Sensed Amplifier Flip Flop (SAFF) is implemented with less than 1ps sampling window to avoid metastability. The current starved delay elements are adopted in the TDC and the conversion resolution is equal to the difference of the delay time from these delay elements. Furthermore, the parallel TDC is realized on layout and finally achieves the resolution of 3ps meanwhile it consumes average power 442 µW with 1. 2V power supply. Measured integral nonlinearity and differential nonlinearity are 0. LSB and 0. 33LSB respectively. Keywords: All Digital PLL, Time to Digital Converter (TDC), Sensed Amplifier Flip Flop (SAFF), Current Starved, Vernier delay line ii Contents ACKNOWLEDGEMENTS †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. i LIST OF FIGURES†¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. iv LIST OF TABLES †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 1. 2. Introduction †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚ ¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 1 State of art †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 4 2. 1 2. 2 2. 3 2. 4 3 Buffer delay line TDC†¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 4 Inverter delay line TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. Vernier TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 5 Gated ring oscillator (GRO) TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 6 System level design †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 7 3. 1 3. 2 3. 3 3. 4 Goal †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ Vernier delay line TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 9 Parallel TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 10 Performance comparison †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 11 4 Schematic design and simulation †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 12 4. 1 Sense Amplifier Based Flip-Flop â € ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 2 Schematic design†¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 14 Sampling window simulation †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 16 4. 1. 1 4. 1. 2 4. 2 Vernier delay line TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 21 Delay cells †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 21 Simulation results †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 5 4. 2. 1 4. 2. 2 4. 3 Parallel TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 28 Delay cells †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 28 Simulation results †¦Ã¢â‚¬ ¦Ã¢â ‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 30 4. 3. 1 4. 3. 2 5 Layout and post-simulation†¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 3 5. 1 5. 2 5. 3 Layout of SAFF and post-simulation †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 33 Layout of parallel TDC and post-simulation †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 35 Comparison and analysis †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã ¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 38 6 7 8 Conclusion †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 0 Future work †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 41 Reference †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 42 iii LIST OF FIGURES Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 iv Effect of LO phase noise in transmitter Block diagram of the phase-domain ADPLL frequency synthesizer Retiming of the reference clock signal (FREF) Operating principle of time-to-digital converter Buffer delay line TDC Inverter delay line TDC Vernier delay line TDC Gated ring oscillator TDC Test bench for measuring rising/falling time of input of TDC Input and output of inverter Diagram of Vernier delay line TDC Timing of the interfaces of Vernier TDC Diagram of parallel TDC Timing of the interfaces o f parallel TDC Symmetric SAFF Schematic of SAFF Schematic of Sense Amplifier Schematic of symmetric SR latch Test bench of SAFF Normal Sampling Case Extreme case of sampling for setup time simulation Extreme case of sampling for hold time simulation Sampling window simulation Current starved delay element Schematic of Matched delay cell Schematic of delay cell 1 Schematic of delay cell 2 Schematic of Vernier delay line TDC Input of Vernier TDC (stop – start) = 0ps Input of Vernier TDC (stop – start) = 20ps Vernier TDC transfer function Vernier TDC linearity Monte Carlo simulation of the resolution for Vernier delay line TDC Delay cell in Parallel TDC Delay time Vs width of transistor T5 Schematic of Parallel TDC Input of parallel TDC (stop – start) = 0ps Input of parallel TDC (stop – start) = 20ps Parallel TDC transfer function Parallel TDC linearity Floor Plan of SAFF Layout of SAFF Post-simulation of sampling window Floor plan of Clock distribution Layo ut of parallel TDC Figure 46 Figure 47 Figure 48 Figure 49 Input of parallel TDC after layout (stop – start) = 0ps Input of parallel TDC after layout (stop – start) = 30ps Parallel TDC transfer function after layout Parallel TDC linearity after layout LIST OF TABLES Table 1 Table 2 Performance comparison between Vernier TDC and parallel TDC Comparison to previous work v 1.Introduction All digital phase locked loop (ADPLL) is employed as frequency synthesizer in radio frequency circuits to create a stable yet tunable local oscillator for transmitters and receivers due to its low power consumption and high integration level. It accepts some frequency reference (FREF) input signal of a very stable frequency of and then generates frequency output as commanded by frequency command word (FCW). The desired frequency of output signal is an FCW multiple of the reference frequency. For an ideal oscillator operating at all power is concentrated around , but the spectrum spreads i nto nearby frequencies in practical situation.This spreading is referred as phase noise which can cause interference in adjacent bands in transmitters and reduce selectivity in receivers [1]. Fig. 1. Effect of LO phase noise in transmitter [1] For example, shown as Fig. 1, when a noiseless receiver must detect a weak desired signal at frequency in the presence of a powerful nearby transmitter generating at frequency with substantial phase noise, the desired signal will be corrupted by phase noise tails of transmitter. Thus the modern radio communication systems require strict specifications about phase noise of synthesizers. In the ADPLL, the time to digital converter (TDC) serves as the phase frequency detector (PFD) meanwhile the digitally controlled Oscillator (DCO) replaces the VCO.The core module is DCO which deliberately avoids analog tuning voltage controls. The DCO is similar to a flip flop whose internal is analog but the analog nature does not propagate beyond the boundari es. Compared to the analog PLL, the loop filter can be implemented in a fully digital manner which will save a large amount of area and maintain low power consumption. 1 Fig. 2. Block diagram of the phase-domain ADPLL frequency synthesizer [2] Fig. 2 shows a type II ADPLL which includes two poles at zero frequency. It has better filtering capabilities of oscillator noise compared to type I ADPLL, leading to improvements in the overall phase noise performance. The ariable phase signal is determined by counting the number of rising clock transitions of the DCO oscillator clock. The reference phase signal is obtained by accumulating the Frequency Command Word (FCW) with every rising edge of the retimed Frequency Reference (FREF) clock. The sampled variable phase is subtracted from the reference phase in a synchronous arithmetic phase detector which is defined by = + ? [k] [2]. Fig. 3. Retiming of the reference clock signal (FREF) [3] 2 There are two asynchronous clock domains, FREF and CKV, and it is difficult to compare the two digital phase values physically at different time instances without facing the metastability problem.During frequency acquisition, their edge relationship is not known, and during phase lock, the edges will exhibit rotation if the fractional FCW is nonzero [1]. Therefore, it is imperative that the digital-word phase comparison should be performed in the same clock domain. This is achieved by retiming process which is performed by oversampling the FREF clock with CKV for synchronization purpose (fig. 3). The retimed clock, CKR is used to synchronize the internal ADPLL operations. However, the retiming process generates a fractional phase error in CKV cycles which is estimated by TDC [3]. The DCO produces phase noise at high frequency, while the TDC determines the in band noise floor [4].The noise contribution of TDC within the loop bandwidth at output of ADPLL is where denotes the delay time of a delay cell in the TDC chain, is the period of RF output and is the frequency of the reference clock [1]. The equation above indicates that a smaller leads to smaller quantization noise from TDC. As a result, the effort is devoted to achieve high resolution TDC in order to obtain low phase noise of ADPLL. Fig. 4. Operating principle of time-to-digital converter [5] Fig. 4 illustrates the principle of time-to-digital converter based on digital delay line. The start signal is delayed by delay elements and sampled by the arrival of the rising edge of stop signal.The sampling process which can be implemented by flip-flops freezes the state of delay line as the stop signal occurs. The outputs of flip-flop will be high value if the start signal passes the delay stages and the sampling process will generate low value if the delay stages have not been passed by start signal. As a result, the position of high to low transition in this thermometer code indicates how far the start signal can be propagated in the interval spanned by star t and stop signal. 3 2. State of art 2. 1 Buffer delay line TDC Fig. 5. Buffer delay line TDC [5] The start signal ripples along the buffer chain and flip-flops are connected to the outputs of buffers. On the arrival of stop signal the state of delay line is sampled by flip-flops.One of the obvious advantages of this TDC is that it can be implemented fully digital. Thus it is simple and compact. However, the resolution is relatively low since it is the delay of one buffer. 2. 2 Inverter delay line TDC Fig. 6. Inverter delay line TDC [5] The resolution in this TDC is the delay of one inverter which is doubled compared to buffers delay chain. In this case, the length of measurement intervals is not indicated by the position of high to low transition but by a phase change of the alternation of high to low sequence. Consequently, the rise and fall delay of inverter should be made equal which requires highly 4 match of the process.In addition, the resolution is still limited by technolog y and therefore not high enough in our application of ADPLL. 2. 3 Vernier TDC Fig. 7. Vernier delay line TDC [6] Vernier delay line TDC is capable of measuring time interval with sub-gate resolution. It consists of two delay lines which delay both start signal and stop signal. The delay in the first line is slightly larger than the delay in the second line. During the measurement, the start signal propagates along the first line and the stop signal occurs later. It seems like the stop signal is chasing start signal. In each stage, it catches up by = Delay1- Delay2 Therefore the resolution is dependent on the difference of two delay stages instead of one delay element.Although the Vernier delay line TDC improves the resolution effectively, the area and power consumption is increased dramatically as the dynamic range becomes larger due to that each stage costs two buffers and one flip-flop. Besides, the conversion time will be increased and in a result it might be not feasible to work in a system. 5 2. 4 Gated ring oscillator (GRO) TDC Fig. 8. Gated ring oscillator TDC [6] The GRO TDC could achieve large dynamic range with small number of delay elements. It measures the number of delay element transitions during measurement interval. By preserving the oscillator state at the end of the measurement interval [k? ], the quantization error [k? 1], from that measurement is also preserved. In fact, when the following measurement of [k? 1] is initiated, the previous quantization error is carried over as [k] = [k? 1]. This results in first-order noise shaping of the quantization error in the frequency domain. Apart from the quantization noise, according to the well-known barrel shift algorithm for dynamic element matching, GRO TDC structure realizes first order shaping of mismatch error [6]. Thus, we can expect that this architecture ideally achieve high resolution without calibration even in the presence of large mismatch. 6 3 System level design 3. 1 GoalThe proposed TDC is designed to work with a 5GHz DCO and a 20MHz reference input while the circuit is fabricated in 65nm IBM CMOS technology; the supply voltage is 1. 2V and development environment is Cadence 6. 1. 3. Fig. 9. Test bench for measuring rising/falling time of input of TDC In order to find out the rising/falling time of the input signal for TDC, the 5GHz sine wave signal which is the same as the output of DCO in ADPLL is put through the inverter with the smallest size and the rising/falling time of the output of inverter is measured (Fig. 9) . 7 Fig. 10. Input and output of inverter Rising/falling time = 16. 58ps. This value is applied to model the practical case of input signals for TDC.The purpose for putting the sinusoid signal generated from DCO passing through the smallest inverter is to model the worst case for TDC with weakest driving ability. As the system level simulation result of ADPLL presents, the dynamic range of TDC is 20ps. The converter resolution is required to be around 2ps meanwhile the power consumption should be kept as low as possible. Since in the application of this ADPLL, sub-gate resolution and small dynamic range are targeted, two kinds of topologies of TDC are proposed. One is Vernier delay line TDC and the other one is parallel TDC. The comparison of these two architectures is concluded and both of them are designed on schematic level. 8 3. 2 Vernier delay line TDCStart Matched delay cell1 EN EN_ Delay1 Delay1 Delay1 Start_ Matched delay cell1 D Q D_ CLK Delay1 D Q0 D_ CLK Delay1 Delay1 D Q26 D_ CLK Stop Fig. 11. Diagram of Vernier delay line TDC 200ps Matched delay cell2 Delay2 Delay2 Delay2 start 20ps stop enable Valid output 2ns TDC_output Fig. 12. Timing of the interfaces of Vernier TDC As the description about Vernier TDC before, the start signal and stop signal are propagated by two delay line with small delay difference each stage respectively. The clock gating technology controlled by enable signal is used to realize low p ower dissipation. The timing relationship of interfaces is described in Fig. 2 which indicates that enable signal should be set to high value half 9 cycle of start signal ahead of the stop rising edge and the conversion time is about 2ns. The delay time of each stage in TDC is about 60ps to 70ps and 27 stages are design to cover the whole dynamic range so that the conservative estimation of conversion time of TDC would be no more than 2ns. The next stage of TDC in ADPLL should sample the output when it is stable. Since the period of FREF is 50ns which means that the instance of measurement occur every 50ns, it is reasonable to adopt the method of serial conversion and prepare the valid output data after 2ns delay. 3. 3Parallel TDC Start Current Staved delay cell EN EN_ Start_ Current Starved delay cell D Q0 D_ CLK Stop Fig. 13. Diagram of parallel TDC Delay1 Delay2 Delay12 D Q1 D_ CLK D Q11 D_ CLK 10 200ps 20ps start stop enable Valid output 420ps TDC_output Fig. 14. Timing of the i nterfaces of parallel TDC Configuring the gates not in a chain but in parallel generates TDC depicted in Fig. 13. The start signal applied to all delay elements in parallel. On the rising of stop signal the outputs of all delay elements are sampled at the same time. Instead of propagating the differential start signal, stop signal is delayed to avoid differential mismatch problem.The delay cells connected to stop signal are sized for delays = 0+? ?N =? . The time difference between the delayed stop signal is quantized with a resolution The conversion results are available immediately after the rising of stop signal. 3. 4 Performance comparison Parallel TDC Parallel delay elements with gradually increasing propagation delays are simultaneously sampled on the arrival of stop signal. No loop structure feasible Sub-gate resolution Conversion time independent from resolution Susceptible to variations Not feasible to high dynamic range Careful layout design Vernier TDC Principle Start and stop signals propagate along two delay lines with slightly different delays.Loop structure Pros Loop structure possible Sub-gate resolution Modular structure High dynamic range possible with loop structure Differential delay lines Conversion time depends on measurement interval and resolution Cons Table1. Performance comparison between Vernier TDC and parallel TDC 11 4 Schematic design and simulation 4. 1 Sense Amplifier Based Flip-Flop Flip-Flops are critical to the performance of Time to Digital Converter due to the tight timing constraints and low power requirements. Metastability is a physical phenomenon that limits the performance of comparators and digital sampling elements, such as latches and flip-flops. It recognizes that it akes a nonzero amount of time from the start of a sampling event to determine the input level or state [15]. This resolution time gets exponentially larger if the input state change gets close to the sampling event. In the limit, if the input changes a t exactly the same time as the sampling event, it might theoretically take an infinite amount of time to resolve. During this time, the output can dwell in an illegal digital state somewhere between zero and one. However, this flip flop is supposed to be reused in ADPLL so that the metastable condition of the retimed reference clock CKR is not acceptable. One reason is that the metastability of any clock could introduce glitches and double clocking in the digital logic circuitry being driven.The other reason is that it is quite likely that within a certain metastability window between FREF and CKV, the clock to Q delay of the flip flop would have the potential to make CKR span multiple DCO clock periods. This amount of uncertainty is not acceptable for proper system operation [4]. For the application of TDC, due to that the metastability sampling window should be no larger than the high resolution to avoid bubbles in TDC code [7], sensed amplifier based flip-flop (SAFF) is chosen. 1 2 VDD MP1 MP2 MP3 MP4 MN3 VDD MN4 D MN1 MN5 MN2 D_ CLK MN6 Pulse Generator Symmetrical SR latch S_ S R VDD R_ MP7 MP8 MP5 MP6 MP9 Q MP10 Q_ MN9 MN10 MN7 MN11 MN12 MN8 Fig. 15. Symmetric SAFF The SAFF shown as Fig. 5 consists of sense amplifier in the first stage and SR latch in the second stage. The amplifier senses complementary differential inputs and produces monotonous transitions from high to low logic level on one of the outputs following the leading clock edge. The SR latch captures each transition and holds the state until the next leading clock arrives [8]. When CLK is low, S_ and R_ are charged to high level through MP1 and MP4 meanwhile MN6 is closed. If D is high, S_ will be discharged through MN3, MN1 and MN6 which is opened by clock leading edges. Accordingly, R_ is hold to high level and Q is high in this case. The additional transistor MN5 is used to provide the discharging patch to ground. For example, when 13 ata is changed as CLK is high which means D is low and D _ is high at this time, S_ would be charging to high level if there is no MN5. However, S_ could be discharged through MN3, MN5, MN2 and MN6 since MN5 provides another path to ground. Although SR latch is able to lock the state of outputs of sense amplifier, MN5 prevents potential charging caused by leakage current even after the input data is changed and therefore guarantee the stable outputs of flip-flop. The SR latch, as the output stage, is kind of symmetric topology with equivalent pull-up and pulldown transistors network. Q+ = S + R_ ·Q Q_+ = R + S_ ·Q_ In the equations above, Q represents a current sate and Q+ represents a future state after the transition of clock.Thus this circuit has equal delays of outputs and provides identical resolution of the rising and falling meta-stability of their input data. In addition, the data input capacitive loading is only one NMOS transistor and the interconnect capacitance parasitic is minimized. 4. 1. 1 Schematic design The basic pri nciples of the SAFF design are that the size of the input transistors should be small enough to minimize the load effect of SAFF and large enough to ensure the speed of it. The PMOS and NMOS networks should be matched and the sizes of transistors are adjusted to obtain equal delay of differential outputs. Fig. 16. Schematic of SAFF 14 Fig. 17. Schematic of Sense Amplifier Fig. 18. Schematic of symmetric SR latch 15 4. 1. 2 Sampling window simulation Fig. 19.Test bench of SAFF The ideal switch is used to initialize the output signal Q otherwise Q will be floating at the beginning of simulation which would result in unpredictable rising or falling edge at the beginning therefore make it difficult to measure a fixed number of signal transition edge. In the practical case, the initial value of inputs of flip flop is either zero or one. The simulation is performed by tuning the delay time of CLK in order to change the time interval between CLK and D/D_. There are several cases simulated to verify the timing constraints of SAFF including setup timing, hold timing and sample window. 1. Normal sampling 16 Fig. 20. Normal Sampling Case Data D changes from zero to one and then is sampled after it is stable for a while. The crossing point of Q and Q_ is around 600mV which means there are equal delay of clock to Q and clock to Q_ due to the symmetric topology of SAFF. 2.Setup time simulation Setup time is the minimum time prior to triggering edge of the clock pulse up to which the data should be kept stable at flip flop input so that data could be properly sampled. This is due to the input capacitance present at the input. It takes some time to charge to the particular logic level at the input. During the simulation, the input data is changing from low to high and high value is supposed to be sampled. Sweep the position of CLK to find out when SAFF cannot capture the correct data. 17 Fig. 21. Extreme case of sampling for setup time simulation The clock to Q delay is incre asing exponentially when input data is approaching the clock triggering edge.When the data comes later than clock edge for 15ps, the clock to Q delay is up to about 280ps shown in Fig. 21. If the data comes even later than this, the output of flip flop will enter into metastable state or will never output high value. 3. Hold time simulation Hold time is the minimum time after the clock edge up to which the data should be kept stable in order to trigger the flip flop at right voltage level. This is the time taken for the various switching elements to transit from saturation to cut off and vice versa. During the simulation, the input data is changing from high to low and high value is supposed to be sampled. Sweep the position of CLK to find out when SAFF cannot capture the correct data. 18 Fig. 22.Extreme case of sampling for hold time simulation The clock to Q delay is increasing exponentially if transition of input data from one to zero happens close to the clock edge. As long as t he data could keep stable long enough the flip flop is capable of recognizing it during limit time interval. The hold timing constraint is that data should be stable after the clock rising at least 16ps (Fig. 22) to guarantee flip-flop could sample the right value otherwise the flip flop will enter into illegal state or never output high value. 4. Sampling window 19 2. 9 2. 8 2. 7 2. 6 x 10 -10 Tclk-Q 2. 5 setup time 2. 4 2. 3 2. 2 2. 1 2 -0. 5 hold time 0 0. 5 1 1. 5 2 Tdata-clk 2. 5 3 3. 5 x 10 4 -11 Fig. 23. Sampling window simulationSampling window is defined as the time interval in which the flip-flop samples the data value. During the interval any change of data is prohibited in order to ensure robust and reliable operation [8]. The flip-flop delay increases as the signal approaches the point of setup and hold time violation until the flip-flop fails to capture the correct data [9] which is displayed in Fig. 23. Metastability is modeled in critical flip-flops by continuous ins pection of the timing relationship between the data input and clock pins and producing an unknown output on the data output pin if the delay to clock skew falls within the forbidden metastable window. Referring to Fig. 3, the metastable window is defined as an x-axis region such that the clock to Q delay on the y-axis is longer by a certain amount than the nominal clock to Q delay. For example, if the nominal clock to Q delay is 200ps when the data to clock timing is far from critical, the metastability window would be 15ps if one can tolerate clock to Q delay increase by 20ps. If one can tolerate a higher clock to Q delay increase of 30ps, the metastable window would drop to 6 ps. A question could be asked as to how far this window can extend. The limitation lies in the fact that for a tight data to clock skew, the noise or other statistical uncertainty, such as jitter, could arbitrarily resolve the output such that the input data is missed.Therefore, for a conventional definition of setup time, not only must the output be free of any metastable condition, but the input data have to be captured correctly. For this reason, the setup and hold times are conservatively defined in standard-cell libraries for an output delay increase of 10 or 20% over nominal. The specific nature of TDC vector capturing does not require this restrictive constraint. Here, any output-level resolution is satisfactory for proper operation as long as it is not metastable at the time of capture, and consequently, 20 the metastable window could be made arbitrarily small [1]. This SAFF demonstrates very narrow sampling window less than 1ps according to the simulation results. 4. 2Vernier delay line TDC There are several components in Vernier delay line TDC including inverter, SAFF, matched delay cell, delay cell 1 and delay cell 2 in which matched delay cell has the same circuit topology with other two delay cells except that it has enable control pins. 4. 2. 1 Delay cells There are severa l methods to implement delay elements. The most popular three methods for designing variable delay cells are shunt capacitor technique, current starved technique and variable transistor technique [10]. In this thesis project, current starved delay element is employed because of its simple structure and relatively wide delay range of regulation.Vdd VBP M4 M2 M6 Vdd in C M1 M5 out VBN M3 Fig. 24. Current starved delay element As can be seen from the Fig. 24, there are two inverters between input and output of this circuit. The charging and discharging currents of the output capacitance of the first inverter, composed of M1and M2, are controlled by the transistors M3 and M4. Charging and discharging currents depend on the bias voltage of M3 and M4 respectively. In this delay element, both rising and 21 falling edges of input signal can be controlled. By increasing/decreasing the effective on resistance of controlling transistor M3 and M4, the circuit delay can be increased /decreased.F ig. 25. Schematic of Matched delay cell As the enable signal is set to high level, the input signal will pass through this delay cell. The enable signal should be set to high level before the active edge of input signal comes. The differential start signal and stop signal passed through this delay cell to produce matched rising/falling edge signal for the next stage in TDC. With respect to design of the size of transistors, the input transistors of the delay cell should be relatively large to shield the load effect of SAFF meanwhile allow T5 to control the changing and discharging current through the capacitors of the first stage of inverter.The second stage of inverter should have enough driving ability for 5GHz input signals and therefore the sizes are specified large enough to withdraw sufficient current from power supply for transition. Due to that the differential signals are delayed, the delay cell is also required to have matched PMOS and NMOS networks to achieve equal delay time for rising or falling input signals. 22 Fig. 26. Schematic of delay cell 1 Fig. 27. Schematic of delay cell 2 23 The only difference between these two delay cells above is the size of transistor T5. The W/L ratio of T5 in delay cell 2 is a bit larger than delay cell 2 makes the delay of delay cell 2 is slightly shorter than delay cell 1. These two delay cells constitute two delay lines for Vernier TDC. Fig. 28.Schematic of Vernier delay line TDC This Vernier TDC includes 27 stages of delay cells for the reason that it should cover the dynamic range of 20ps and the additional offset value introduced by the setup timing of SAFF. The first dumpy stage of delay cell is used to match the differential input signals for the following delay lines so that the input signals for each stage are characterized with the same rising or falling time. As a result, the delay difference between each delay pair for start and stop signal is only dependent on the different size of transistors in the current starved delay cell. 24 4. 2. 2 Simulation results The input of Vernier TDC, the delay difference between the start and stop signal, is swept from 0 to 20ps.The resolution and linearity are calculated and analyzed by conversion results from TDC. Fig. 29. Input of Vernier TDC (stop – start) = 0ps Fig. 30. Input of Vernier TDC (stop – start) = 20ps 25 The offset value of this TDC is 8 observed from Fig. 29. The result shown in Fig. 30 indicates that the start signal has passed through 22 stages of delay cells as the input is 20ps. Resolution = (20ps – 0ps)/ (22 – 8) = 1. 43ps 25 20 Output of Vernier TDC (ps) 15 10 5 0 0 2 4 6 8 10 12 14 Input of Vernier TDC (ps) 16 18 20 Fig. 31. Vernier TDC transfer function 0. 6 0. 4 0. 2 DNL and INL [LSB] 0 -0. 2 -0. 4 -0. 6 -0. 8 -1 INL DNL 0 2 4 6 8 10 12 Input of Vernier TDC 14 16 18 20 Fig. 32. Vernier TDC linearity 26The Differential Non Linearity (DNL) is the deviation in the difference between two successiv e threshold points from 1LSB. Integral Non Linearity (INL) is the deviation of the actual output. Both of them are calculated and reported in Fig. 32. The maximum DNL is +0. 4LSB while the maximum INL is -0. 89LSB. The process (skew) parameter files in the model directory contain the definition of the statistical distributions that represent the main process variations for the technology. This gives designers the capability of testing their designs under many different process variations to ensure that their circuits perform as desired throughout the entire range of process specifications. This is a Monte Carlo approach to the checking of designs.While being the most accurate test, it can also be time consuming to run enough simulations to obtain a valid statistical sample. Fig. 33. Monte Carlo simulation of the resolution for Vernier delay line TDC When running Monte Carlo to include FET mismatch, BOTH the Spectre mismatch and process vary statements are active. This will turn on b oth process and mismatch variations. Spectre provides the unique capability of running process variations independent of mismatch variations. This capability is not supported for this release. The average resolution calculated by averaging the delay difference between two delay lines is around 1. 66ps. The average power over one period is 148. 1E-6 W.The maximum power consumption is about 3. 6mW and the conversion time is around 2ns which is in accordance with the interfacing time estimation in system level design. Since the enable signal closed the TDC after the conversion is completed, the start signal with high frequency is prohibited to propagate so as to eliminate the unnecessary transition of delay cells and in a result saving the power dissipation. 27 4. 3 4. 3. 1 Parallel TDC Delay cells In order to design a serial of delay cells with the equal difference of delay time used in parallel TDC, the size of the transistor in a current starved structure is swept. Fig. 34. Delay ce ll in Parallel TDC 28Fig. 35. Delay time Vs width of transistor T5 Unlike Vernier TDC, only stop signal is delayed by various delay cells in parallel TDC. Thus the control of rising edge required, and then the size of transistor T5 is adjusted. As can be seen from Fig. 34, the size of transistors M1, M2, M4 and M5 is basically determined by the load capacitance which refers to the CLK pin of SAFF in this situation. Transistor T5 should be much smaller than M2 so that the discharging current could be controlled by T5. As the size of T5 increases, the delay time becomes smaller which means the delay cell is faster. According to the parameter analysis result in Fig. 5, the size of T5 can be determined by selecting the size corresponding to the delay time with 2ps difference for a serial delay cells. Fig. 36. Schematic of Parallel TDC 29 As the analysis in system level design, the delay cells are sized for delays = 0 + ? ?N. The single stop signal is delayed in parallel TDC, therefore t he matched delay cell connected to differential start signal is used to cancel the 0 and offset value. 4. 3. 2 Simulation results Similarly to Vernier TDC simulation, the input of parallel TDC, the delay difference between the start and stop signal, is swept from 0 to 20ps. The resolution and linearity are calculated and analyzed by conversion results from TDC. Fig. 37.Input of parallel TDC (stop – start) = 0ps 30 Fig. 38. Input of parallel TDC (stop – start) = 20ps The offset value of this TDC is 1 observed from Fig. 37. The result shown in Fig. 38 indicates that the start signal has passed through 11 stages of delay cells as the input is 20ps. Resolution = (20ps – 0ps)/ (11 – 1) = 2ps. 20 18 16 Output of parallel TDC (ps) 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 Input of parallel TDC (ps) 16 18 20 Fig. 39. Parallel TDC transfer function 31 1 INL DNL DNL and INL [LSB] 0. 5 0 -0. 5 0 2 4 6 8 10 12 Input of parallel TDC 14 16 18 20 Fig. 40. Parallel TDC linea rity DNL and INL are calculated and reported in Fig. 40. The maximum DNL is +0. LSB while the maximum INL is 1LSB. The average power over one period is 87. 33E-6 W which is much smaller than Vernier TDC. The reason is that the clock gating technology controlled by enable signal eliminates the redundant transition of delay cells. As the system level design indicates, the parallel TDC only works for 420ps each period of stop signal because that the conversion is completed instantly due to the intrinsic characteristic of parallel TDC and therefore there is no power consumption during the rest time. Although the peak power consumption is approximately equivalent to Vernier TDC, the average power dissipation is decreased dramatically. 32 Layout and post-simulation 5. 1 Layout of SAFF and post-simulation For the layout of radio frequency circuit the interconnection parasitic will be a critical problem. In an audio application for instance parasitic will probably be a minor concern. Howeve r, the operation frequency of this circuit is 5GHz which means that the interconnection parasitic will influence the performance of circuit dramatically. To minimize this influence, we could move interconnections to higher metals and make the metals carry current rather than poly. Besides, the floor plan should be as compact as possible to optimize the parasitic and impedance of interconnections. GND T0Symmetric SR Latch T15 T14 T13 T8 T9 T5 T3 Q_ T1 T12 T10 T11 T7 Q T6 T4 T2 VDD T0 T2 T4 T3 T5 T9 T1 D T6 T7 D_ CLK T8 CLK GND Sensed Amplifier Fig. 41. Floor Plan of SAFF 33 There are several steps for floor plan. First step is to examine the size of transistors and split transistor size in a number of layout oriented fingers. Then identify the transistors than can be placed on the same stack according to the principles of using almost the same number of fingers per stack and put the transistors with common drain or source together. In the floor plan shown in Fig. 41, power line VDD i s reused by SR latch and sensed amplifier to make the connections compact.Fig. 42. Layout of SAFF 34 In the development environment of Cadence 6. 1. 3, Calibre is used for DRC and Assura is used to do LVS check and RCX. Post-simulation is then performed with av_extracted view. Fig. 43. Post-simulation of sampling window Compared to Fig. 23, Fig. 43 illustrates that the timing constraint point moved from 16ps to 29ps which will affect the offset value of TDC. In addition, the delay time from clock leading edge to output Q is increased. However, this SAFF after layout can be employed to avoid meta-stability effectively due to that the sampling window is still less than 1ps. 5. 2 Layout of parallel TDC and post-simulationIn this TDC system, the clock distribution network formed as a tree distributes the signal to all the delay cells. To reduce the clock uncertainty, the network requires highly matched topology showed as Fig. 44 below. 35 Clock Fig. 44. Floor plan of Clock distribution This kind of topology guarantees the equal delay from the common point clock to each element. Fig. 45. Layout of parallel TDC After DRC and LVS, the RC net list is extracted to do post-simulation. The input of parallel TDC after layout, the delay difference between the start and stop signal, is swept from 0 to 30ps. The resolution and linearity are calculated and analyzed by conversion results from TDC. Fig. 46.Input of parallel TDC after layout (stop – start) = 0ps 36 Fig. 47. Input of parallel TDC after layout (stop – start) = 30ps The offset value of this implemented TDC is 0 observed from Fig. 46. The result shown in Fig. 47 indicates that the start signal has passed through 10 stages of delay cells as the input is 30ps. Resolution = (30ps – 0ps)/ (10 – 0) = 3ps. 35 30 Output of parallel TDC after layout (ps) 25 20 15 10 5 0 0 5 10 15 20 Input of parallel TDC after layout (ps) 25 30 Fig. 48. Parallel TDC transfer function after layout 37 0. 5 0. 4 0. 3 DNL and INL after layout [LSB] 0. 2 0. 1 0 -0. 1 -0. 2 -0. 3 -0. 4 -0. 5 INL DNL 0 5 10 15 20 Input of parallel TDC (ps) 25 30 Fig. 49.Parallel TDC linearity after layout DNL and INL are calculated and reported in Fig. 49. The maximum DNL is 0. 33LSB while the maximum INL is 0. 5LSB. The average power over one period is 442. 1E-6 W. The maxim total current is about 3. 24mA. The peak power consumption is almost the same as the TDC before layout, but there are obvious ripples even the TDC is disabled due to that the parasitic capacitors increase the time for charging and discharging. 5. 3 Comparison and analysis Technique Parallel 2-level DL parallel Pseudo-diff DL VernierGRO CMOS [ µm] 0. 065 0. 35 0. 13 0. 09 0. 09 Supply [V] 1. 2 3 1. 2 1. 3 1. 2 Power [mW] 3. 89 50 2. 5 6. 9 4. 32 Resolution [ps] 3 24 12 17 6. 4 INL/DNL 0. 5/0. 3 -1. 5/0. 55 -1. 15/1 0. 7/0. 7 – Work This [12] [3] [7] [13] Table2. Comparison to previous work Table2 compares the proposed TDC to prior pub lished work in CMOS technology. This TDC features the fastest resolution with the best linearity. The power consumption is not directly comparable because the results from the other works are corresponding to different input range. However, it still indicates that this TDC consumes very low power due to that the start signal 38 only passes two buffers and the stop signal with low frequency is delayed. The TDC error has several components: quantization, linearity and randomness due to thermal effects.As can be seen from table5, the implemented TDC achieves medium linearity which can be improved if the layout is enhanced from floor plan considering the parasitic effects. With respect to quantization noise, the total noise power generated from this kind of TDC is spread uniformly over the span from dc to the Nyquist frequency without modulation. As a result, the proposed TDC contributes the lowest noise floor due to high resolution. = =3ps, , = 20MHz, we obtain = -104. 3 dBc/Hz. Banerj ee’s figure of merit (BFM) [14], being a 1-Hz normalized phase noise floor, is defined as BFM = where is a sampling frequency of the phase comparison and N= is the frequency division ratio of a PLL.It is used to compare the phase performance of PLLs with different reference frequencies and division ratios. In this TDC based ADPLL, BFM = -225. 3dB. Even though state-of-the-art conventional PLLs implemented in a SiGe process can outperform the ADPLL presented here in the in band phase noise, -213 dB in reference and -218 dB in reference, the worst case BFM of -205 dB appears adequate even for GSM applications, since there are no other significant phase-noise contributions as in the conventional PLLs [4]. However, the Gated Ring Oscillator TDC is able to push most of the noise to high frequency region which is then filtered by the loop filter in ADPLL through holding oscillation node state between measurements.The obvious drawback of this TDC is that the dynamic range is relativ ely small which will limit the application of it. Parallel TDC is not feasible to compose the loop structure so that the area and power dissipation will be increased dramatically if larger dynamic range is required. But the Vernier TDC designed in this thesis can be used in the loop structure for large dynamic range. 39 6 Conclusion In this thesis, two kinds of Time to Digital Converters are designed with Vernier and parallel structure on schematic level respectively. The performance of these two TDCs are concluded and compared. In the Vernier TDC, only two delay cells are designed and then reused to constitute two delay lines with slightly different delay time.This architecture is easy to implement and reduces the mismatch with delay cells. But the conversion time dependent on resolution and measurement interval time is relatively long since the signals are propagating along the delay cells in serial. On the other hand, in parallel TDC, the process of conversion is completed instan taneously due to that the signals are passing through the delay cells and then captured in parallel. Thus it has lower average power dissipation over one period. However, a set of delay cells are designed which obviously introduce nonlinearities. To minimize the mismatch problem, the single stop signal is delayed instead of two input signals for avoiding the differential mismatch situation.To sum up, both of the TDCs achieve sub-gate resolution which is able to meet the application requirements and Vernier TDC has higher resolution and better linearity but longer conversion time and larger power consumption compared to parallel TDC according to the simulation results. The parallel TDC is chosen to be implemented on layout. Comparing the results from schematic simulation and post-simulation, the performance is decreased on resolution, linearity and power consumption after layout. The major reason for this phenomenon is the parasitic capacitance of transistors and real wires which is a significant factor to affect the final properties in high frequency circuits.In the stage of schematic design, the sizes of transistors are not fully considered and results in difficulties on floor plan of layout. Specifically, the transistors are rather difficult to split into the same fingers per stack and therefore the floor plan is not compact enough to minimize the interconnections. Besides, the parasitic capacitance should have been emulated on schematic simulation in order to predict the effect after layout otherwise it would be very time consuming if the schematic design is modified after layout. In addition, the size of transistors is very small which makes them comparable to wire parasitic effects. Although small transistors are with smaller parasitic capacitance and less power consumption, they will more sensitive to layout mismatch.The function of the TDCs designed and implemented in the thesis is guaranteed for the application but the performance needs to be improved. The layout turns out to be an essential stage for the final characteristics of the circuits. With a more thoughtful design flow and sophisticated consideration for mismatch, the circuits after layout could maintain the performance as schematic level. 40 7 Future work There is plenty of more work to be done to improve the performance of TDC. Due to that the TDC is essential to the aggressive goal of phase noise from all digital PLL, other kinds of architectures of it are worth to try for the required resolution and dynamic range. Since the performance of circuit after layout is not identical with schematic, the size of transistors could be modified for layout oriented. To reduce the parasitic effects, layout should be improved from a better floor plan. Vernier TDC with higher resolution and better linearity could be implemented on layout which can tolerate first order PVT variation if two delay chains are well matched [11]. Although the Vernier TDC and parallel TDC achieve high reso lution, they have very low efficiency when measuring large time intervals, which requires extra hardware and power consumption. To overcome this limitation, a Vernier Ring TDC has been proposed recently.Unlike the conventional Vernier TDC, this novel TDC places the Vernier delay cells in a ring format such that the delay chains can be reused for measuring large time intervals. Digital logic monitors the number of laps the signals propagate along the rings. Arbiters are used to record the location where the lag signal catches up with the lead signal. The reuse of Vernier delay cells in a ring configuration achieves fine resolution and large detectable range simultaneously with small area and low power consumption [11]. This architecture of Vernier Ring TDC combines the Vernier delay lines and GRO topology is worth to implement for wide application. ? ? 41 8 [1] [2] [3] [4] [5] [6] [7]